Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects
This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA be...
| Autores: | ; ; ; ; |
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| Tipo de documento: | Artículo |
| Fecha de publicación: | 2008 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Lenguaje: | Inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/2028 |
| Acceso en línea: | https://hdl.handle.net/2117/2028 |
| Nivel de acceso: | Acceso abierto |
| Palabra clave: | Power amplifiers Radio frequency Multi-LUT predistortion Power amplifier linearization Amplificadors de potència Radiofreqüència Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Radiocomunicació i exploració electromagnètica |
| _version_ | 1878741428909113344 |
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| author | Gilabert Pinal, Pere Lluís|||0000-0001-6183-6977 |
| author2 | Cesari Bohigas, Albert Montoro López, Gabriel|||0000-0002-1328-4175 Bertran Albertí, Eduardo|||0000-0002-6960-7527 Dilhac, Jean Marie |
| author2_role | author author author author |
| author_browse | Bertran Albertí, Eduardo|||0000-0002-6960-7527 Cesari Bohigas, Albert Dilhac, Jean Marie Gilabert Pinal, Pere Lluís|||0000-0001-6183-6977 Montoro López, Gabriel|||0000-0002-1328-4175 |
| author_facet | Gilabert Pinal, Pere Lluís|||0000-0001-6183-6977 Cesari Bohigas, Albert Montoro López, Gabriel|||0000-0002-1328-4175 Bertran Albertí, Eduardo|||0000-0002-6960-7527 Dilhac, Jean Marie |
| author_role | author |
| collection | UPCommons. Portal del coneixement obert de la UPC |
| description | This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | ES_e504e20ad4035e2f1f9416bf767fb0ce |
| institution | Universitat Politècnica de Catalunya (UPC) |
| instname_str | Universitat Politècnica de Catalunya (UPC) |
| language | eng |
| network_acronym_str | ES |
| network_name_str | España |
| oai_identifier_str | oai:upcommons.upc.edu:2117/2028 |
| publishDate | 2008 |
| publishDateSort | 2008 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| publisherStr | Institute of Electrical and Electronics Engineers (IEEE) |
| reponame_str | UPCommons. Portal del coneixement obert de la UPC |
| spelling | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects Gilabert Pinal, Pere Lluís|||0000-0001-6183-6977 Cesari Bohigas, Albert Montoro López, Gabriel|||0000-0002-1328-4175 Bertran Albertí, Eduardo|||0000-0002-6960-7527 Dilhac, Jean Marie Power amplifiers Radio frequency Multi-LUT predistortion Power amplifier linearization Amplificadors de potència Radiofreqüència Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Radiocomunicació i exploració electromagnètica This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects. Peer Reviewed Institute of Electrical and Electronics Engineers (IEEE) https://hdl.handle.net/2117/2028 |
| spellingShingle | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects Gilabert Pinal, Pere Lluís|||0000-0001-6183-6977 Power amplifiers Radio frequency Multi-LUT predistortion Power amplifier linearization Amplificadors de potència Radiofreqüència Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Radiocomunicació i exploració electromagnètica |
| title | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects |
| title_full | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects |
| title_fullStr | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects |
| title_full_unstemmed | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects |
| title_short | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects |
| title_sort | Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects |
| topic | Power amplifiers Radio frequency Multi-LUT predistortion Power amplifier linearization Amplificadors de potència Radiofreqüència Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Radiocomunicació i exploració electromagnètica |
| topic_facet | Power amplifiers Radio frequency Multi-LUT predistortion Power amplifier linearization Amplificadors de potència Radiofreqüència Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Radiocomunicació i exploració electromagnètica |
| url | https://hdl.handle.net/2117/2028 |