Gilabert Pinal, P. L., Cesari Bohigas, A., Montoro López, G., Bertran Albertí, E., & Dilhac, J. M. (2008). Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects. Institute of Electrical and Electronics Engineers (IEEE).
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Cita Chicago Style (17a ed.)
Gilabert Pinal, Pere Lluís|||0000-0001-6183-6977, Albert Cesari Bohigas, Gabriel|||0000-0002-1328-4175 Montoro López, Eduardo|||0000-0002-6960-7527 Bertran Albertí, y Jean Marie Dilhac. Multi Look-up Table FPGA Implementation of an Adaptive Digital Predistorter for Linearizing RF Power Amplifiers with Memory Effects. Institute of Electrical and Electronics Engineers (IEEE), 2008.
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Cita MLA (9a ed.)
Gilabert Pinal, Pere Lluís|||0000-0001-6183-6977, et al. Multi Look-up Table FPGA Implementation of an Adaptive Digital Predistorter for Linearizing RF Power Amplifiers with Memory Effects. Institute of Electrical and Electronics Engineers (IEEE), 2008.
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