A Verilog HDL digital architecture for delay calculation
A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of...
| Authors: | ; ; ; |
|---|---|
| Format: | Article |
| Status: | Published version |
| Publication date: | 2007 |
| Country: | Argentina |
| Institution: | Consejo Nacional de Investigaciones Científicas y Técnicas |
| Repository: | CONICET Digital (CONICET) |
| Language: | English |
| OAI Identifier: | oai:ri.conicet.gov.ar:11336/105848 |
| Online Access: | http://hdl.handle.net/11336/105848 |
| Access Level: | Open access |
| Keyword: | VERILOG FPGA LOW POWER DIGITAL CMOS VLSI https://purl.org/becyt/ford/2.2 https://purl.org/becyt/ford/2 |
| _version_ | 1878403809726693376 |
|---|---|
| author | Chacón-Rodríguez, A. |
| author2 | Martín-Pirchio, F. N. Julian, Pedro Marcelo Mandolesi, Pablo Sergio |
| author2_role | author author author |
| author_browse | Chacón-Rodríguez, A. Julian, Pedro Marcelo Mandolesi, Pablo Sergio Martín-Pirchio, F. N. |
| author_facet | Chacón-Rodríguez, A. Martín-Pirchio, F. N. Julian, Pedro Marcelo Mandolesi, Pablo Sergio |
| author_role | author |
| collection | CONICET Digital (CONICET) |
| description | A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | AR_c4635cec0f1ea495a289d075dafa35d8 |
| identifier_str_mv | Chacón-Rodríguez, A.; Martín-Pirchio, F. N.; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; A Verilog HDL digital architecture for delay calculation; Planta Piloto de Ingeniería Química; Latin American Applied Research; 37; 1; 2-2007; 41-45 0327-0793 1851-8796 CONICET Digital CONICET |
| institution | Consejo Nacional de Investigaciones Científicas y Técnicas |
| instname_str | Consejo Nacional de Investigaciones Científicas y Técnicas |
| language | eng |
| network_acronym_str | AR |
| network_name_str | Argentina |
| oai_identifier_str | oai:ri.conicet.gov.ar:11336/105848 |
| publishDate | 2007 |
| publishDateSort | 2007 |
| publisher | Planta Piloto de Ingeniería Química |
| publisherStr | Planta Piloto de Ingeniería Química |
| reponame_str | CONICET Digital (CONICET) |
| spelling | A Verilog HDL digital architecture for delay calculation Chacón-Rodríguez, A. Martín-Pirchio, F. N. Julian, Pedro Marcelo Mandolesi, Pablo Sergio VERILOG FPGA LOW POWER DIGITAL CMOS VLSI https://purl.org/becyt/ford/2.2 https://purl.org/becyt/ford/2 A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations. Fil: Chacón-Rodríguez, A.. Universidad de Mar del Plata. Laboratorio de Componentes Electrónicos; Argentina Fil: Martín-Pirchio, F. N.. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; Argentina Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina Fil: Mandolesi, Pablo Sergio. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; Argentina Planta Piloto de Ingeniería Química http://hdl.handle.net/11336/105848 Chacón-Rodríguez, A.; Martín-Pirchio, F. N.; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; A Verilog HDL digital architecture for delay calculation; Planta Piloto de Ingeniería Química; Latin American Applied Research; 37; 1; 2-2007; 41-45 0327-0793 1851-8796 CONICET Digital CONICET |
| spellingShingle | A Verilog HDL digital architecture for delay calculation Chacón-Rodríguez, A. VERILOG FPGA LOW POWER DIGITAL CMOS VLSI https://purl.org/becyt/ford/2.2 https://purl.org/becyt/ford/2 |
| status_str | publishedVersion |
| title | A Verilog HDL digital architecture for delay calculation |
| title_full | A Verilog HDL digital architecture for delay calculation |
| title_fullStr | A Verilog HDL digital architecture for delay calculation |
| title_full_unstemmed | A Verilog HDL digital architecture for delay calculation |
| title_short | A Verilog HDL digital architecture for delay calculation |
| title_sort | A Verilog HDL digital architecture for delay calculation |
| topic | VERILOG FPGA LOW POWER DIGITAL CMOS VLSI https://purl.org/becyt/ford/2.2 https://purl.org/becyt/ford/2 |
| topic_facet | VERILOG FPGA LOW POWER DIGITAL CMOS VLSI https://purl.org/becyt/ford/2.2 https://purl.org/becyt/ford/2 |
| url | http://hdl.handle.net/11336/105848 |