A Verilog HDL digital architecture for delay calculation
A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of...
| Authors: | ; ; ; |
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| Format: | Article |
| Status: | Published version |
| Publication date: | 2007 |
| Country: | Argentina |
| Institution: | Consejo Nacional de Investigaciones Científicas y Técnicas |
| Repository: | CONICET Digital (CONICET) |
| Language: | English |
| OAI Identifier: | oai:ri.conicet.gov.ar:11336/105848 |
| Online Access: | http://hdl.handle.net/11336/105848 |
| Access Level: | Open access |
| Keyword: | VERILOG FPGA LOW POWER DIGITAL CMOS VLSI https://purl.org/becyt/ford/2.2 https://purl.org/becyt/ford/2 |
| Summary: | A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations. |
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