Secured V2X communication using optimized prime field ECC architecture
The objective of this research is to ensure a high level of security in various forms of vehicular communication (V2V, V2I, and V2N) and to support vehicles in safely receiving all keys and messages from Roadside Unit (RSU), other vehicles, or the network with the support of simple cryptographic tec...
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| Tipo de documento: | Artículo |
| Estado: | Published version |
| Fecha de publicación: | 2024 |
| País: | México |
| Institución: | UNAM |
| Repositorio: | Journal of Applied Research and Technology |
| Lenguaje: | Inglés |
| OAI Identifier: | oai:ojs2.localhost:article/2230 |
| Acceso en línea: | https://jart.icat.unam.mx/index.php/jart/article/view/2230 |
| Nivel de acceso: | Acceso abierto |
| Palabra clave: | Elliptic Curve Cryptography Point Multiplication Montgomery Left to Right algorithm Karatsuba |
| Sumario: | The objective of this research is to ensure a high level of security in various forms of vehicular communication (V2V, V2I, and V2N) and to support vehicles in safely receiving all keys and messages from Roadside Unit (RSU), other vehicles, or the network with the support of simple cryptographic techniques. Elliptic Curve Cryptography (ECC) is one of the many cryptographic techniques that offer a desirable response to this requirement. The Koblitz curve secp256k1 is supported by the designed ECC processor for 256-bit point multiplication and point addition. A powerful illustration of the "Divide and Conquer" strategy's ability to accelerate multiplication asymptotically is given by the Karatsuba algorithm. The ECC processor's multiplication operation is accelerated further by the incorporation of pipelining. With a maximum clock frequency of 238.40MHz, the proposed Karatsuba-based ECC processor executes 256-bit single point multiplication in 0.937ms, providing 273.21kbps throughput, and taking up 8.42k slices in a Virtex-7 FPGA. Scalar multiplication is extended by incorporating a pipeline by increasing the highest clock frequency by up to 7.97%, which decreases time consumption by 9.90% and boosts throughput by 10.99%. In terms of area, operating frequency, area-delay product, and throughput, the suggested pipelined Karatsuba multiplier based ECC processor performs better than the existing designs. |
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