Systems for fractional sampling rate conversion
This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and progra...
| Author: | |
|---|---|
| Format: | Master's thesis |
| Status: | Accepted version |
| Publication date: | 2007 |
| Country: | México |
| Institution: | INAOE |
| Repository: | Repositorio Institucional del INAOE |
| Language: | English |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/645 |
| Online Access: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645 |
| Access Level: | Open access |
| Keyword: | info:eu-repo/classification/Radio de software/Software radio info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips info:eu-repo/classification/Comunicación digital/Digital communication info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330706 |
| _version_ | 1878407553851850752 |
|---|---|
| author | NAINA RAO NAGRALE |
| author_browse | NAINA RAO NAGRALE |
| author_facet | NAINA RAO NAGRALE |
| author_role | author |
| collection | Repositorio Institucional del INAOE |
| description | This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and programmable logic devices (PLDs). Then, the basic principles of Sampling Rate Conversion (SRC) is presented, including various methods for decimation and their impacts on the filter complexity. Further, a review of the Finite Impulse Response (FIR) filters has been done, along with the methods of rounding and sharpening for efficient filter design. The raising technique, block filtering and time varying polyphase structures are also revised. Overview of existing sampling rate conversion filters has been presented, which includes Cascaded Integrated Comb (CIC) filter, Polynomial filter and Time Varying CIC filter. Using multirate techniques and polyphase representation, a simple method of designing fractional sampling rate conversion system based on the Interpolated Finite Impulse Response (IFIR) filter has been proposed. Finally, the proposed algorithm is simulated in MATLAB and implemented in the SPARTAN 3 family of the Xilinx’s Field Programmable Gate Array (FPGA) using project navigator Xilinx ISE 8.2i. The input and output of the implemented structure is verified in Symphony EDA Sonata 3.1. All the proposed MATLAB functions and VHDL programs are included in Appendix. |
| eu_rights_str_mv | openAccess |
| format | masterThesis |
| id | MX_03c6dfe8bb7e2d77eb3304116a1ad2fa |
| institution | INAOE |
| instname_str | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| language | eng |
| network_acronym_str | MX |
| network_name_str | México |
| oai_identifier_str | oai:inaoe.repositorioinstitucional.mx:1009/645 |
| publishDate | 2007 |
| publishDateSort | 2007 |
| publisher | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| publisherStr | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| reponame_str | Repositorio Institucional del INAOE |
| spelling | Systems for fractional sampling rate conversion NAINA RAO NAGRALE info:eu-repo/classification/Radio de software/Software radio info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips info:eu-repo/classification/Comunicación digital/Digital communication info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330706 This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and programmable logic devices (PLDs). Then, the basic principles of Sampling Rate Conversion (SRC) is presented, including various methods for decimation and their impacts on the filter complexity. Further, a review of the Finite Impulse Response (FIR) filters has been done, along with the methods of rounding and sharpening for efficient filter design. The raising technique, block filtering and time varying polyphase structures are also revised. Overview of existing sampling rate conversion filters has been presented, which includes Cascaded Integrated Comb (CIC) filter, Polynomial filter and Time Varying CIC filter. Using multirate techniques and polyphase representation, a simple method of designing fractional sampling rate conversion system based on the Interpolated Finite Impulse Response (IFIR) filter has been proposed. Finally, the proposed algorithm is simulated in MATLAB and implemented in the SPARTAN 3 family of the Xilinx’s Field Programmable Gate Array (FPGA) using project navigator Xilinx ISE 8.2i. The input and output of the implemented structure is verified in Symphony EDA Sonata 3.1. All the proposed MATLAB functions and VHDL programs are included in Appendix. La Presente tesis trata el diseño de filtros de decimación para sistemas de conversión de la razón de muestreo fraccional utilizable en Software Radio. En principio se presenta una introducción general de la tecnología Software Radio incluyendo arquitectura, técnicas de multirazon y dispositivos lógicos programables. Posteriormente, se muestran los principios básicos de conversión de muestreo así como los métodos de decimación y su impacto en la complejidad de filtros. Además, se presenta una revisión de los filtros, FIR ( Respuesta al impulso Finita), incluyendo los métodos redondeo y afilado para el diseño eficiente de filtros, técnicas de elevación y métodos block filtering. Una vista general de filtros de razón de muestreo existentes es presentada, la cual contiene los filtros Cascaded Integrated Comb (CIC) Filtro, filtro Polynomial, and Time varying CIC Filter. Se propone un método simple de diseño de un sistema de conversión de la razón de muestreo fraccional basada en filtros Interpolated Finite Impulse Response (IFIR) usando técnicos multirazon y representación polifase. Finalmente, el algoritmo propuesta es simulado en MATLAB e implementado mediante SPARTAN 3 familia de Field Programmable Gate Array (FPGA) usando navegador Xilinx ISE 8.2i. La entrada y la salida de la estructura implementada es verificada en Symphony EDA Sonata 3.1. Todas las funciones MATLAB propuestas y las programas VHDL son incluidos en el Apéndice. Instituto Nacional de Astrofísica, Óptica y Electrónica http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645 |
| spellingShingle | Systems for fractional sampling rate conversion NAINA RAO NAGRALE info:eu-repo/classification/Radio de software/Software radio info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips info:eu-repo/classification/Comunicación digital/Digital communication info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330706 |
| status_str | acceptedVersion |
| title | Systems for fractional sampling rate conversion |
| title_full | Systems for fractional sampling rate conversion |
| title_fullStr | Systems for fractional sampling rate conversion |
| title_full_unstemmed | Systems for fractional sampling rate conversion |
| title_short | Systems for fractional sampling rate conversion |
| title_sort | Systems for fractional sampling rate conversion |
| topic | info:eu-repo/classification/Radio de software/Software radio info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips info:eu-repo/classification/Comunicación digital/Digital communication info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330706 |
| topic_facet | info:eu-repo/classification/Radio de software/Software radio info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips info:eu-repo/classification/Comunicación digital/Digital communication info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330706 |
| url | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645 |