A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs
| Authors: | ; ; ; ; ; |
|---|---|
| Format: | Article |
| Publication date: | 2017 |
| Country: | España |
| Institution: | Universidad Politécnica de Madrid |
| Repository: | Archivo Digital UPM |
| OAI Identifier: | oai:oa.upm.es:85786 |
| Online Access: | https://oa.upm.es/85786/ |
| Access Level: | Open access |
| Keyword: | —inFET III-V CMOS |
| Description not available. |