Analysis and simulation of data prefetching algorithms for last-level cache memory
Analysis and simulation of data prefetching algorithms for last-level cache memory. Analysis and comparison of one of the latest data prefetching algorithms in terms of performance, network utilization and prefetching accuracy.
| Author: | |
|---|---|
| Format: | Master's thesis |
| Publication date: | 2018 |
| Country: | España |
| Institution: | Universitat Politècnica de Catalunya (UPC) |
| Repository: | UPCommons. Portal del coneixement obert de la UPC |
| Language: | English |
| OAI Identifier: | oai:upcommons.upc.edu:2117/123664 |
| Online Access: | https://hdl.handle.net/2117/123664 |
| Access Level: | Open access |
| Keyword: | Computer architecture Memory hierarchy (Computer science) prerecerca memòria cau prerecerca de dades prefetching cache memory data prefetching Arquitectura d'ordinadors Jerarquia de memòria (Informàtica) Àrees temàtiques de la UPC::Informàtica |
| _version_ | 1878737012355235840 |
|---|---|
| author | Escuín Blasco, Carlos |
| author_browse | Escuín Blasco, Carlos |
| author_facet | Escuín Blasco, Carlos |
| author_role | author |
| collection | UPCommons. Portal del coneixement obert de la UPC |
| description | Analysis and simulation of data prefetching algorithms for last-level cache memory. Analysis and comparison of one of the latest data prefetching algorithms in terms of performance, network utilization and prefetching accuracy. |
| eu_rights_str_mv | openAccess |
| format | masterThesis |
| id | ES_99017404b95205f0729980a4e929b1a3 |
| institution | Universitat Politècnica de Catalunya (UPC) |
| instname_str | Universitat Politècnica de Catalunya (UPC) |
| language | eng |
| network_acronym_str | ES |
| network_name_str | España |
| oai_identifier_str | oai:upcommons.upc.edu:2117/123664 |
| publishDate | 2018 |
| publishDateSort | 2018 |
| publisher | Universitat Politècnica de Catalunya |
| publisherStr | Universitat Politècnica de Catalunya |
| reponame_str | UPCommons. Portal del coneixement obert de la UPC |
| spelling | Analysis and simulation of data prefetching algorithms for last-level cache memory Escuín Blasco, Carlos Computer architecture Memory hierarchy (Computer science) prerecerca memòria cau prerecerca de dades prefetching cache memory data prefetching Arquitectura d'ordinadors Jerarquia de memòria (Informàtica) Àrees temàtiques de la UPC::Informàtica Analysis and simulation of data prefetching algorithms for last-level cache memory. Analysis and comparison of one of the latest data prefetching algorithms in terms of performance, network utilization and prefetching accuracy. Universitat Politècnica de Catalunya https://hdl.handle.net/2117/123664 |
| spellingShingle | Analysis and simulation of data prefetching algorithms for last-level cache memory Escuín Blasco, Carlos Computer architecture Memory hierarchy (Computer science) prerecerca memòria cau prerecerca de dades prefetching cache memory data prefetching Arquitectura d'ordinadors Jerarquia de memòria (Informàtica) Àrees temàtiques de la UPC::Informàtica |
| title | Analysis and simulation of data prefetching algorithms for last-level cache memory |
| title_full | Analysis and simulation of data prefetching algorithms for last-level cache memory |
| title_fullStr | Analysis and simulation of data prefetching algorithms for last-level cache memory |
| title_full_unstemmed | Analysis and simulation of data prefetching algorithms for last-level cache memory |
| title_short | Analysis and simulation of data prefetching algorithms for last-level cache memory |
| title_sort | Analysis and simulation of data prefetching algorithms for last-level cache memory |
| topic | Computer architecture Memory hierarchy (Computer science) prerecerca memòria cau prerecerca de dades prefetching cache memory data prefetching Arquitectura d'ordinadors Jerarquia de memòria (Informàtica) Àrees temàtiques de la UPC::Informàtica |
| topic_facet | Computer architecture Memory hierarchy (Computer science) prerecerca memòria cau prerecerca de dades prefetching cache memory data prefetching Arquitectura d'ordinadors Jerarquia de memòria (Informàtica) Àrees temàtiques de la UPC::Informàtica |
| url | https://hdl.handle.net/2117/123664 |